Lets Get Physical: Inside The PhysX Physics Processor

No details about the internal structure of the PhysX physics processor have been released, however there is a patent [patent] which describes the ideas behind the processor.  The patent itself is a very difficult read as it is describes in detail, a number of complex subject areas in a legalistic style.  This is par for the course for patents but just to make life more difficult it uses seemingly no end of three letter acronyms to describe the various parts of the design. Here’s an example:

“FPE 19 comprises, for example, four Vector Processing Engines (VPE), 19a, 19b, 19c, and 19d,

instead of the configuration shown in FIG. 11, including a SIU, and a plurality of SFU and VFU units. DME

18 further comprises a Switch Fabric 150, five Memory Control Units (MCU, 151a through 151d and 152),

PCI 34 and MIU 50.”

Many of these are not explained at the first use so you have to hunt for the explanation and “ODE”, is not explained at all, perhaps an “Obfuscated Description Elucidator”?  (“Ordinary Differential Equation” in case you’re wondering).

However, hidden in all that is a description of not one, but two potential designs for a physics processor and the software which runs on it (software concepts are described in part 1).  I shall mostly concentrate on describing the second variant of the hardware as it is described as the “presently preferred embodiment”, i.e. this is the version more likely to be built.  Unfortunately I’ll have to use a few three letter acronyms myself but not too many.

Inside The PPU

The PhysX PPU (Physics Processor Unit) chip is made up of 3 engines along with its own memory controller, PCI interface and various I/O ports.

The three engines are:

PCE - PPU Control Engine

DME - Data Movement Engine

FPE - Floating Point Engine

To put it simply:

The PCE controls everything.

The DME moves data in and out of memory.

The FPE does floating point calculations.

The PCE is a conventional RISC processor, which processor is completely unknown but it’s used for tasks which require little computation or bandwidth so it’s not going to be anything exciting.  There are no end of CPU cores available which can be used for this purpose (MIPS, ARM and PowerPC are 3 possible choices but there are many more).  There’s really not much to be said about the PCE as its job is really just to manage the DME and FPE by uploading their programs to them and communicating with the rest of the system.

Both the DME and FPE contain many blocks of RAM.  These are discrete blocks of RAM and are probably not mapped into the main system’s memory.  They will also not be caches, caches take up more room than a block of plain RAM and would have little benefit in this processor, in fact due to the complexity involved using cache in this processor would most likely be a major disadvantage.